1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
24 - description: external DVP
30 - const: noc_bus_isp_axi
35 - description: ISP Top core
36 - description: ISP Top Axi
37 - description: NOC ISP Bus
42 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
47 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
64 additionalProperties: false
68 #include <dt-bindings/clock/starfive,jh7110-crg.h>
69 #include <dt-bindings/power/starfive,jh7110-pmu.h>
70 #include <dt-bindings/reset/starfive,jh7110-crg.h>
72 ispcrg: clock-controller@19810000 {
73 compatible = "starfive,jh7110-ispcrg";
74 reg = <0x19810000 0x10000>;
75 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
76 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
77 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
79 clock-names = "isp_top_core", "isp_top_axi",
80 "noc_bus_isp_axi", "dvp_clk";
81 resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
82 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
83 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
86 power-domains = <&pwrc JH7110_PD_ISP>;