Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
   8
   9 maintainers:
  10   - Xingyu Wu <xingyu.wu@starfivetech.com>
  11
  12 properties:
  13   compatible:
  14     const: starfive,jh7110-ispcrg
  15
  16   reg:
  17     maxItems: 1
  18
  19   clocks:
  20     items:
  21       - description: ISP Top core
  22       - description: ISP Top Axi
  23       - description: NOC ISP Bus
  24       - description: external DVP
  25
  26   clock-names:
  27     items:
  28       - const: isp_top_core
  29       - const: isp_top_axi
  30       - const: noc_bus_isp_axi
  31       - const: dvp_clk
  32
  33   resets:
  34     items:
  35       - description: ISP Top core
  36       - description: ISP Top Axi
  37       - description: NOC ISP Bus
  38
  39   '#clock-cells':
  40     const: 1
  41     description:
  42       See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
  43
  44   '#reset-cells':
  45     const: 1
  46     description:
  47       See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
  48
  49   power-domains:
  50     maxItems: 1
  51     description:
  52       ISP domain power
  53
  54 required:
  55   - compatible
  56   - reg
  57   - clocks
  58   - clock-names
  59   - resets
  60   - '#clock-cells'
  61   - '#reset-cells'
  62   - power-domains
  63
  64 additionalProperties: false
  65
  66 examples:
  67   - |
  68     #include <dt-bindings/clock/starfive,jh7110-crg.h>
  69     #include <dt-bindings/power/starfive,jh7110-pmu.h>
  70     #include <dt-bindings/reset/starfive,jh7110-crg.h>
  71
  72     ispcrg: clock-controller@19810000 {
  73         compatible = "starfive,jh7110-ispcrg";
  74         reg = <0x19810000 0x10000>;
  75         clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
  76                  <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
  77                  <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
  78                  <&dvp_clk>;
  79         clock-names = "isp_top_core", "isp_top_axi",
  80                       "noc_bus_isp_axi", "dvp_clk";
  81         resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
  82                  <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
  83                  <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
  84         #clock-cells = <1>;
  85         #reset-cells = <1>;
  86         power-domains = <&pwrc JH7110_PD_ISP>;
  87     };