1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
24 - description: STG AXI/AHB
25 - description: APB Bus
26 - description: GMAC0 GTX
29 - description: Main Oscillator (24 MHz)
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
31 - description: STG AXI/AHB or GMAC0 RGMII RX
32 - description: APB Bus or STG AXI/AHB
33 - description: GMAC0 GTX or APB Bus
34 - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
37 - description: Main Oscillator (24 MHz)
38 - description: GMAC0 RMII reference
39 - description: GMAC0 RGMII RX
40 - description: STG AXI/AHB
41 - description: APB Bus
42 - description: GMAC0 GTX
43 - description: RTC Oscillator (32.768 kHz)
61 - const: gmac0_rmii_refin
62 - const: gmac0_rgmii_rxin
71 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
76 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
86 additionalProperties: false
90 #include <dt-bindings/clock/starfive,jh7110-crg.h>
92 clock-controller@17000000 {
93 compatible = "starfive,jh7110-aoncrg";
94 reg = <0x17000000 0x10000>;
95 clocks = <&osc>, <&gmac0_rmii_refin>,
97 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
98 <&syscrg JH7110_SYSCLK_APB_BUS>,
99 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
101 clock-names = "osc", "gmac0_rmii_refin",
102 "gmac0_rgmii_rxin", "stg_axiahb",
103 "apb_bus", "gmac0_gtxclk",