1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2022 Unisoc Inc.
5 $id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: UMS512 Soc clock controller
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - sprd,ums512-apahb-gate
20 - sprd,ums512-aonapb-clk
21 - sprd,ums512-pmu-gate
26 - sprd,ums512-aon-gate
27 - sprd,ums512-audcpapb-gate
28 - sprd,ums512-audcpahb-gate
31 - sprd,ums512-mm-gate-clk
32 - sprd,ums512-apapb-gate
41 The input parent clock(s) phandle for the clock, only list
42 fixed clocks which are declared in devicetree.
60 additionalProperties: false
64 ap_clk: clock-controller@20200000 {
65 compatible = "sprd,ums512-ap-clk";
66 reg = <0x20200000 0x1000>;
68 clock-names = "ext-26m";