1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
20 All available clocks are defined as preprocessor macros in
21 include/dt-bindings/clock/exynos7-clk.h header.
26 - samsung,exynos7-clock-topc
27 - samsung,exynos7-clock-top0
28 - samsung,exynos7-clock-top1
29 - samsung,exynos7-clock-ccore
30 - samsung,exynos7-clock-peric0
31 - samsung,exynos7-clock-peric1
32 - samsung,exynos7-clock-peris
33 - samsung,exynos7-clock-fsys0
34 - samsung,exynos7-clock-fsys1
35 - samsung,exynos7-clock-mscl
36 - samsung,exynos7-clock-aud
62 const: samsung,exynos7-clock-top0
71 - const: dout_sclk_bus0_pll
72 - const: dout_sclk_bus1_pll
73 - const: dout_sclk_cc_pll
74 - const: dout_sclk_mfc_pll
75 - const: dout_sclk_aud_pll
84 const: samsung,exynos7-clock-top1
93 - const: dout_sclk_bus0_pll
94 - const: dout_sclk_bus1_pll
95 - const: dout_sclk_cc_pll
96 - const: dout_sclk_mfc_pll
105 const: samsung,exynos7-clock-ccore
114 - const: dout_aclk_ccore_133
123 const: samsung,exynos7-clock-peric0
132 - const: dout_aclk_peric0_66
142 const: samsung,exynos7-clock-peric1
151 - const: dout_aclk_peric1_66
171 const: samsung,exynos7-clock-peris
180 - const: dout_aclk_peris_66
189 const: samsung,exynos7-clock-fsys0
198 - const: dout_aclk_fsys0_200
199 - const: dout_sclk_mmc2
208 const: samsung,exynos7-clock-fsys1
217 - const: dout_aclk_fsys1_200
218 - const: dout_sclk_mmc0
219 - const: dout_sclk_mmc1
220 - const: dout_sclk_ufsunipro20
221 - const: dout_sclk_phy_fsys1
222 - const: dout_sclk_phy_fsys1_26m
231 const: samsung,exynos7-clock-aud
240 - const: fout_aud_pll
245 additionalProperties: false
249 #include <dt-bindings/clock/exynos7-clk.h>
252 compatible = "fixed-clock";
253 clock-output-names = "fin_pll";
255 clock-frequency = <24000000>;
258 clock-controller@105e0000 {
259 compatible = "samsung,exynos7-clock-top1";
260 reg = <0x105e0000 0xb000>;
263 <&clock_topc DOUT_SCLK_BUS0_PLL>,
264 <&clock_topc DOUT_SCLK_BUS1_PLL>,
265 <&clock_topc DOUT_SCLK_CC_PLL>,
266 <&clock_topc DOUT_SCLK_MFC_PLL>;
267 clock-names = "fin_pll",
268 "dout_sclk_bus0_pll",
269 "dout_sclk_bus1_pll",