1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "oscclk" - PLL input clock from XXTI
20 All available clocks are defined as preprocessor macros in
21 include/dt-bindings/clock/exynos5433.h header.
26 # CMU_TOP which generates clocks for
27 # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
29 - samsung,exynos5433-cmu-top
30 # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
31 - samsung,exynos5433-cmu-cpif
32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
33 - samsung,exynos5433-cmu-mif
34 # CMU_PERIC which generates clocks for
35 # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
36 - samsung,exynos5433-cmu-peric
37 # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
38 - samsung,exynos5433-cmu-peris
39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
40 - samsung,exynos5433-cmu-fsys
41 - samsung,exynos5433-cmu-g2d
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
43 - samsung,exynos5433-cmu-disp
44 - samsung,exynos5433-cmu-aud
45 - samsung,exynos5433-cmu-bus0
46 - samsung,exynos5433-cmu-bus1
47 - samsung,exynos5433-cmu-bus2
48 - samsung,exynos5433-cmu-g3d
49 - samsung,exynos5433-cmu-gscl
50 - samsung,exynos5433-cmu-apollo
51 # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
52 # CoreSight and L2 cache controller
53 - samsung,exynos5433-cmu-atlas
54 # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
56 - samsung,exynos5433-cmu-mscl
57 - samsung,exynos5433-cmu-mfc
58 - samsung,exynos5433-cmu-hevc
59 # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
60 - samsung,exynos5433-cmu-isp
61 # CMU_CAM0 which generates clocks for
62 # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
63 - samsung,exynos5433-cmu-cam0
64 # CMU_CAM1 which generates clocks for
65 # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
66 - samsung,exynos5433-cmu-cam1
67 # CMU_IMEM which generates clocks for SSS (Security SubSystem) and
69 - samsung,exynos5433-cmu-imem
98 const: samsung,exynos5433-cmu-top
107 - const: sclk_mphy_pll
108 - const: sclk_mfc_pll
109 - const: sclk_bus_pll
118 const: samsung,exynos5433-cmu-cpif
135 const: samsung,exynos5433-cmu-mif
144 - const: sclk_mphy_pll
153 const: samsung,exynos5433-cmu-fsys
162 - const: sclk_ufs_mphy
163 - const: aclk_fsys_200
164 - const: sclk_pcie_100_fsys
165 - const: sclk_ufsunipro_fsys
166 - const: sclk_mmc2_fsys
167 - const: sclk_mmc1_fsys
168 - const: sclk_mmc0_fsys
169 - const: sclk_usbhost30_fsys
170 - const: sclk_usbdrd30_fsys
179 const: samsung,exynos5433-cmu-g2d
188 - const: aclk_g2d_266
189 - const: aclk_g2d_400
198 const: samsung,exynos5433-cmu-disp
207 - const: sclk_dsim1_disp
208 - const: sclk_dsim0_disp
209 - const: sclk_dsd_disp
210 - const: sclk_decon_tv_eclk_disp
211 - const: sclk_decon_vclk_disp
212 - const: sclk_decon_eclk_disp
213 - const: sclk_decon_tv_vclk_disp
214 - const: aclk_disp_333
223 const: samsung,exynos5433-cmu-aud
232 - const: fout_aud_pll
241 const: samsung,exynos5433-cmu-bus0
249 - const: aclk_bus0_400
258 const: samsung,exynos5433-cmu-bus1
266 - const: aclk_bus1_400
275 const: samsung,exynos5433-cmu-bus2
284 - const: aclk_bus2_400
293 const: samsung,exynos5433-cmu-g3d
302 - const: aclk_g3d_400
311 const: samsung,exynos5433-cmu-gscl
320 - const: aclk_gscl_111
321 - const: aclk_gscl_333
330 const: samsung,exynos5433-cmu-apollo
339 - const: sclk_bus_pll_apollo
348 const: samsung,exynos5433-cmu-atlas
357 - const: sclk_bus_pll_atlas
366 const: samsung,exynos5433-cmu-mscl
375 - const: sclk_jpeg_mscl
376 - const: aclk_mscl_400
385 const: samsung,exynos5433-cmu-mfc
394 - const: aclk_mfc_400
403 const: samsung,exynos5433-cmu-hevc
412 - const: aclk_hevc_400
421 const: samsung,exynos5433-cmu-isp
430 - const: aclk_isp_dis_400
431 - const: aclk_isp_400
440 const: samsung,exynos5433-cmu-cam0
449 - const: aclk_cam0_333
450 - const: aclk_cam0_400
451 - const: aclk_cam0_552
460 const: samsung,exynos5433-cmu-cam1
469 - const: sclk_isp_uart_cam1
470 - const: sclk_isp_spi1_cam1
471 - const: sclk_isp_spi0_cam1
472 - const: aclk_cam1_333
473 - const: aclk_cam1_400
474 - const: aclk_cam1_552
483 const: samsung,exynos5433-cmu-imem
492 - const: aclk_imem_sssx_266
493 - const: aclk_imem_266
494 - const: aclk_imem_200
499 additionalProperties: false
503 #include <dt-bindings/clock/exynos5433.h>
505 compatible = "fixed-clock";
506 clock-output-names = "oscclk";
508 clock-frequency = <24000000>;
511 clock-controller@10030000 {
512 compatible = "samsung,exynos5433-cmu-top";
513 reg = <0x10030000 0x1000>;
516 clock-names = "oscclk",
521 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
522 <&cmu_mif CLK_SCLK_MFC_PLL>,
523 <&cmu_mif CLK_SCLK_BUS_PLL>;