1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5260 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
19 - "xrtcxti" - input clock from XRTCXTI
20 - "ioclk_pcm_extclk" - pcm external operation clock
21 - "ioclk_spdif_extclk" - spdif external operation clock
22 - "ioclk_i2s_cdclk" - i2s0 codec clock
25 There are several clocks which are generated by specific PHYs. These clocks
26 are fed into the clock controller and then routed to the hardware blocks.
27 These clocks are defined as fixed clocks in the driver with following names::
28 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
29 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
30 - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
31 - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
32 - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
33 - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
34 - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
35 - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
36 - "phyclk_dptx_phy_clk_div2"
37 - "phyclk_mipi_dphy_4l_m_rxclkesc0"
38 - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
39 - "phyclk_usbhost20_phy_freeclk"
40 - "phyclk_usbhost20_phy_clk48mohci"
41 - "phyclk_usbdrd30_udrd30_pipe_pclk"
42 - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
44 All available clocks are defined as preprocessor macros in
45 include/dt-bindings/clock/exynos5260-clk.h header.
50 - samsung,exynos5260-clock-top
51 - samsung,exynos5260-clock-peri
52 - samsung,exynos5260-clock-egl
53 - samsung,exynos5260-clock-kfc
54 - samsung,exynos5260-clock-g2d
55 - samsung,exynos5260-clock-mif
56 - samsung,exynos5260-clock-mfc
57 - samsung,exynos5260-clock-g3d
58 - samsung,exynos5260-clock-fsys
59 - samsung,exynos5260-clock-aud
60 - samsung,exynos5260-clock-isp
61 - samsung,exynos5260-clock-gscl
62 - samsung,exynos5260-clock-disp
88 const: samsung,exynos5260-clock-top
99 - const: dout_media_pll
108 const: samsung,exynos5260-clock-peri
117 - const: ioclk_pcm_extclk
118 - const: ioclk_i2s_cdclk
119 - const: ioclk_spdif_extclk
120 - const: phyclk_hdmi_phy_ref_cko
121 - const: dout_aclk_peri_66
122 - const: dout_sclk_peri_uart0
123 - const: dout_sclk_peri_uart1
124 - const: dout_sclk_peri_uart2
125 - const: dout_sclk_peri_spi0_b
126 - const: dout_sclk_peri_spi1_b
127 - const: dout_sclk_peri_spi2_b
128 - const: dout_aclk_peri_aud
137 const: samsung,exynos5260-clock-egl
146 - const: dout_bus_pll
155 const: samsung,exynos5260-clock-kfc
164 - const: dout_media_pll
173 const: samsung,exynos5260-clock-g2d
182 - const: dout_aclk_g2d_333
191 const: samsung,exynos5260-clock-mif
208 const: samsung,exynos5260-clock-mfc
217 - const: dout_aclk_mfc_333
226 const: samsung,exynos5260-clock-g3d
243 const: samsung,exynos5260-clock-fsys
252 - const: phyclk_usbhost20_phy_phyclock
253 - const: phyclk_usbhost20_phy_freeclk
254 - const: phyclk_usbhost20_phy_clk48mohci
255 - const: phyclk_usbdrd30_udrd30_pipe_pclk
256 - const: phyclk_usbdrd30_udrd30_phyclock
257 - const: dout_aclk_fsys_200
266 const: samsung,exynos5260-clock-aud
275 - const: fout_aud_pll
276 - const: ioclk_i2s_cdclk
277 - const: ioclk_pcm_extclk
286 const: samsung,exynos5260-clock-isp
295 - const: dout_aclk_isp1_266
296 - const: dout_aclk_isp1_400
297 - const: mout_aclk_isp1_266
307 const: samsung,exynos5260-clock-gscl
316 - const: dout_aclk_gscl_400
317 - const: dout_aclk_gscl_333
326 const: samsung,exynos5260-clock-disp
335 - const: phyclk_dptx_phy_ch3_txd_clk
336 - const: phyclk_dptx_phy_ch2_txd_clk
337 - const: phyclk_dptx_phy_ch1_txd_clk
338 - const: phyclk_dptx_phy_ch0_txd_clk
339 - const: phyclk_hdmi_phy_tmds_clko
340 - const: phyclk_hdmi_phy_ref_clko
341 - const: phyclk_hdmi_phy_pixel_clko
342 - const: phyclk_hdmi_link_o_tmds_clkhi
343 - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
344 - const: phyclk_dptx_phy_o_ref_clk_24m
345 - const: phyclk_dptx_phy_clk_div2
346 - const: phyclk_mipi_dphy_4l_m_rxclkesc0
347 - const: phyclk_hdmi_phy_ref_cko
348 - const: ioclk_spdif_extclk
349 - const: dout_aclk_peri_aud
350 - const: dout_aclk_disp_222
351 - const: dout_sclk_disp_pixel
352 - const: dout_aclk_disp_333
357 additionalProperties: false
361 #include <dt-bindings/clock/exynos5260-clk.h>
364 compatible = "fixed-clock";
365 clock-output-names = "fin_pll";
367 clock-frequency = <24000000>;
370 clock-controller@10010000 {
371 compatible = "samsung,exynos5260-clock-top";
372 reg = <0x10010000 0x10000>;
375 <&clock_mif MIF_DOUT_MEM_PLL>,
376 <&clock_mif MIF_DOUT_BUS_PLL>,
377 <&clock_mif MIF_DOUT_MEDIA_PLL>;
378 clock-names = "fin_pll",