1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3588 Family Clock and Reset Control Module
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3588 clock controller generates the clock and also implements a reset
15 controller for SoC peripherals. For example it provides SCLK_UART2 and
16 PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. All available clock and reset IDs
20 are defined as preprocessor macros in dt-binding headers.
47 assigned-clock-rates: true
50 $ref: /schemas/types.yaml#/definitions/phandle
52 phandle to the syscon managing the "general register files". It is used
53 for GRF muxes, if missing any muxes present in the GRF will not be
62 additionalProperties: false
66 cru: clock-controller@fd7c0000 {
67 compatible = "rockchip,rk3588-cru";
68 reg = <0xfd7c0000 0x5c000>;