1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3188/RK3066 clock controller generates and supplies clocks to various
15 controllers within the SoC and also implements a reset controller for SoC
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. All available clocks are defined as
19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
21 Similar macros exist for the reset sources in these files.
22 There are several clocks that are generated outside the SoC. It is expected
23 that they are defined using standard clock bindings with following
25 - "xin24m" - crystal input - required
26 - "xin32k" - RTC clock - optional
27 - "xin27m" - 27mhz crystal input on RK3066 - optional
28 - "ext_hsadc" - external HSADC clock - optional
29 - "ext_cif0" - external camera clock - optional
30 - "ext_rmii" - external RMII clock - optional
31 - "ext_jtag" - external JTAG clock - optional
36 - rockchip,rk3066a-cru
38 - rockchip,rk3188a-cru
56 $ref: /schemas/types.yaml#/definitions/phandle
58 Phandle to the syscon managing the "general register files" (GRF),
59 if missing pll rates are not changeable, due to the missing pll
68 additionalProperties: false
72 cru: clock-controller@20000000 {
73 compatible = "rockchip,rk3188-cru";
74 reg = <0x20000000 0x1000>;
75 rockchip,grf = <&grf>;