1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3126/RK3128 clock controller generates and supplies clock to various
15 controllers within the SoC and also implements a reset controller for SoC
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume. All available clocks are defined as
19 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
20 used in device tree sources. Similar macros exist for the reset sources in
54 $ref: /schemas/types.yaml#/definitions/phandle
56 Phandle to the syscon managing the "general register files" (GRF),
57 if missing pll rates are not changeable, due to the missing pll
66 additionalProperties: false
70 cru: clock-controller@20000000 {
71 compatible = "rockchip,rk3128-cru";
72 reg = <0x20000000 0x1000>;
73 rockchip,grf = <&grf>;