1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile EV2 System Management Unit
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
41 Function block with an input mux and a divider, which corresponds to
42 "Serial clock generator" in fig. "Clock System Overview" of the manual,
43 and "xxx frequency division setting register" (XXXCLKDIV) registers.
44 This makes internal (neither input nor output) clock that is provided
45 to input of xxxGCLK block.
49 const: renesas,emev2-smu-clkdiv
54 Byte offset from SMU base and Bit position in the register.
69 additionalProperties: false
75 Clock gating node shown as "Clock stop processing block" in the
76 fig. "Clock System Overview" of the manual.
77 Registers are "xxx clock gate control register" (XXXGCLKCTRL).
81 const: renesas,emev2-smu-gclk
86 Byte offset from SMU base and Bit position in the register.
100 additionalProperties: false
102 additionalProperties: true
106 // Example of clock-tree description:
108 // This describes a clock path in the clock tree
109 // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
111 compatible = "renesas,emev2-smu";
112 reg = <0xe0110000 0x10000>;
113 #address-cells = <2>;
117 compatible = "fixed-clock";
118 clock-frequency = <32768>;
122 compatible = "fixed-factor-clock";
128 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
129 compatible = "renesas,emev2-smu-clkdiv";
134 usia_u0_sclk: usia_u0_sclk@4a0,1 {
135 compatible = "renesas,emev2-smu-gclk";
137 clocks = <&usia_u0_sclkdiv>;