1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
14 includes PLLs, and fixed and variable ratio dividers.
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
40 clock-output-names: true
43 description: Board-specific settings of the MD_CK* bits on R-Mobile A1
44 $ref: /schemas/types.yaml#/definitions/uint32
48 '#power-domain-cells':
63 const: renesas,r8a73a4-cpg-clocks
94 const: renesas,r8a7740-cpg-clocks
100 - description: extal2
101 - description: extalr
130 const: renesas,r8a7778-cpg-clocks
150 const: renesas,r8a7779-cpg-clocks
171 const: renesas,r7s72100-cpg-clocks
176 - description: extal1
177 - description: usb_x1
189 const: renesas,sh73a0-cpg-clocks
194 - description: extal1
195 - description: extal2
220 - renesas,r8a7778-cpg-clocks
221 - renesas,r8a7779-cpg-clocks
222 - renesas,rz-cpg-clocks
225 - '#power-domain-cells'
227 additionalProperties: false
231 #include <dt-bindings/clock/r8a7740-clock.h>
232 cpg_clocks: cpg_clocks@e6150000 {
233 compatible = "renesas,r8a7740-cpg-clocks";
234 reg = <0xe6150000 0x10000>;
235 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
238 "usb24s", "i", "zg", "b", "m1", "hp", "hpp",
239 "usbp", "s", "zb", "m3", "cp";
240 renesas,mode = <0x05>;