1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
6 which can then be passed to a variety of internal logic, including
7 cores and peripheral IP blocks.
8 Please refer to the Reference Manual for details.
10 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11 which the chip complies.
13 Chassis Version Example Chips
14 --------------- -------------
15 1.0 p4080, p5020, p5040
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
31 * "fsl,t4240-clockgen"
32 * "fsl,b4420-clockgen"
33 * "fsl,b4860-clockgen"
34 * "fsl,ls1012a-clockgen"
35 * "fsl,ls1021a-clockgen"
36 Chassis-version clock strings include:
37 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
38 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
39 - reg: Describes the address of the device's resources within the
40 address space defined by its parent bus, and resource zero
41 represents the clock register set
44 - ranges: Allows valid translation between child's address space and
45 parent's. Must be present if the device has sub-nodes.
46 - #address-cells: Specifies the number of cells used to represent
47 physical base addresses. Must be present if the device has
48 sub-nodes and set to 1 if present
49 - #size-cells: Specifies the number of cells used to represent
50 the size of an address. Must be present if the device has
51 sub-nodes and set to 1 if present
52 - clock-frequency: Input system clock frequency (SYSCLK)
53 - clocks: If clock-frequency is not specified, sysclk may be provided
54 as an input clock. Either clock-frequency or clocks must be
59 The clockgen node should act as a clock provider, though in older device
60 trees the children of the clockgen node are the clock providers.
62 When the clockgen node is a clock provider, #clock-cells = <2>.
63 The first cell of the clock specifier is the clock type, and the
64 second cell is the clock index for the specified type.
68 1 cmux index (n in CLKCnCSR)
69 2 hwaccel index (n in CLKCGnHWACSR)
70 3 fman 0 for fm1, 1 for fm2
71 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
75 clockgen: global-utilities@e1000 {
76 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
77 clock-frequency = <133333333>;
78 reg = <0xe1000 0x1000>;
84 clocks = <&clockgen 3 0>;
90 NOTE: These nodes are deprecated. Kernels should continue to support
91 device trees with these nodes, but new device trees should not use them.
93 Most of the bindings are from the common clock binding[1].
94 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
97 - compatible : Should include one of the following:
98 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
99 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
100 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
101 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
102 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
103 It takes parent's clock-frequency as its clock.
104 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
105 It takes parent's clock-frequency as its clock.
106 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
107 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
108 - #clock-cells: From common clock binding. The number of cells in a
109 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
110 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
111 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
112 clock-specifier cell may take the following values:
113 * 0 - equal to the PLL frequency
114 * 1 - equal to the PLL frequency divided by 2
115 * 2 - equal to the PLL frequency divided by 4
117 Recommended properties:
118 - clocks: Should be the phandle of input parent clock
119 - clock-names: From common clock binding, indicates the clock name
120 - clock-output-names: From common clock binding, indicates the names of
122 - reg: Should be the offset and length of clock block base address.
123 The length should be 4.
127 clockgen: global-utilities@e1000 {
128 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
129 ranges = <0x0 0xe1000 0x1000>;
130 clock-frequency = <133333333>;
131 reg = <0xe1000 0x1000>;
132 #address-cells = <1>;
137 compatible = "fsl,qoriq-sysclk-1.0";
138 clock-output-names = "sysclk";
144 compatible = "fsl,qoriq-core-pll-1.0";
146 clock-output-names = "pll0", "pll0-div2";
152 compatible = "fsl,qoriq-core-pll-1.0";
154 clock-output-names = "pll1", "pll1-div2";
160 compatible = "fsl,qoriq-core-mux-1.0";
161 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
162 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
163 clock-output-names = "cmux0";
169 compatible = "fsl,qoriq-core-mux-1.0";
170 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
171 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
172 clock-output-names = "cmux1";
175 platform-pll: platform-pll@c00 {
178 compatible = "fsl,qoriq-platform-pll-1.0";
180 clock-output-names = "platform-pll", "platform-pll-div2";
185 Example for legacy clock consumer:
188 cpu0: PowerPC,e5500@0 {