1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 Qualcomm display clock control module provides the clocks, resets and power
17 See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
26 - description: Board XO source
27 - description: Board Always On XO source
28 - description: Display's AHB clock
29 - description: sleep clock
30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
38 - description: Link clock from DP PHY2
39 - description: VCO DIV clock from DP PHY2
40 - description: Link clock from DP PHY3
41 - description: VCO DIV clock from DP PHY3
49 '#power-domain-cells':
57 A phandle and PM domain specifier for the MMCX power domain.
62 A phandle to an OPP node describing required MMCX performance point.
71 - '#power-domain-cells'
73 additionalProperties: false
77 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
78 #include <dt-bindings/clock/qcom,rpmh.h>
79 #include <dt-bindings/power/qcom,rpmhpd.h>
80 clock-controller@af00000 {
81 compatible = "qcom,sm8550-dispcc";
82 reg = <0x0af00000 0x10000>;
83 clocks = <&rpmhcc RPMH_CXO_CLK>,
84 <&rpmhcc RPMH_CXO_CLK_A>,
85 <&gcc GCC_DISP_AHB_CLK>,
101 #power-domain-cells = <1>;
102 power-domains = <&rpmhpd RPMHPD_MMCX>;
103 required-opps = <&rpmhpd_opp_low_svs>;