1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller on SM8450
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm video clock control module provides the clocks, resets and power
16 See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
29 - description: Board XO source
30 - description: Video AHB clock from GCC
40 A phandle to an OPP node describing required MMCX performance point.
48 '#power-domain-cells':
59 - '#power-domain-cells'
61 additionalProperties: false
65 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
66 #include <dt-bindings/clock/qcom,rpmh.h>
67 #include <dt-bindings/power/qcom,rpmhpd.h>
68 videocc: clock-controller@aaf0000 {
69 compatible = "qcom,sm8450-videocc";
70 reg = <0x0aaf0000 0x10000>;
71 clocks = <&rpmhcc RPMH_CXO_CLK>,
72 <&gcc GCC_VIDEO_AHB_CLK>;
73 power-domains = <&rpmhpd RPMHPD_MMCX>;
74 required-opps = <&rpmhpd_opp_low_svs>;
77 #power-domain-cells = <1>;