Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display Clock & Reset Controller for SM8450
   8
   9 maintainers:
  10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11
  12 description: |
  13   Qualcomm display clock control module which supports the clocks, resets and
  14   power domains on SM8450.
  15
  16   See also:
  17     include/dt-bindings/clock/qcom,sm8450-dispcc.h
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - qcom,sm8450-dispcc
  23
  24   clocks:
  25     minItems: 3
  26     items:
  27       - description: Board XO source
  28       - description: Board Always On XO source
  29       - description: Display's AHB clock
  30       - description: sleep clock
  31       - description: Byte clock from DSI PHY0
  32       - description: Pixel clock from DSI PHY0
  33       - description: Byte clock from DSI PHY1
  34       - description: Pixel clock from DSI PHY1
  35       - description: Link clock from DP PHY0
  36       - description: VCO DIV clock from DP PHY0
  37       - description: Link clock from DP PHY1
  38       - description: VCO DIV clock from DP PHY1
  39       - description: Link clock from DP PHY2
  40       - description: VCO DIV clock from DP PHY2
  41       - description: Link clock from DP PHY3
  42       - description: VCO DIV clock from DP PHY3
  43
  44   '#clock-cells':
  45     const: 1
  46
  47   '#reset-cells':
  48     const: 1
  49
  50   '#power-domain-cells':
  51     const: 1
  52
  53   reg:
  54     maxItems: 1
  55
  56   power-domains:
  57     description:
  58       A phandle and PM domain specifier for the MMCX power domain.
  59     maxItems: 1
  60
  61   required-opps:
  62     description:
  63       A phandle to an OPP node describing required MMCX performance point.
  64     maxItems: 1
  65
  66 required:
  67   - compatible
  68   - reg
  69   - clocks
  70   - '#clock-cells'
  71   - '#reset-cells'
  72   - '#power-domain-cells'
  73
  74 additionalProperties: false
  75
  76 examples:
  77   - |
  78     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
  79     #include <dt-bindings/clock/qcom,rpmh.h>
  80     #include <dt-bindings/power/qcom-rpmpd.h>
  81     clock-controller@af00000 {
  82       compatible = "qcom,sm8450-dispcc";
  83       reg = <0x0af00000 0x10000>;
  84       clocks = <&rpmhcc RPMH_CXO_CLK>,
  85                <&rpmhcc RPMH_CXO_CLK_A>,
  86                <&gcc GCC_DISP_AHB_CLK>,
  87                <&sleep_clk>,
  88                <&dsi0_phy 0>,
  89                <&dsi0_phy 1>,
  90                <&dsi1_phy 0>,
  91                <&dsi1_phy 1>;
  92       #clock-cells = <1>;
  93       #reset-cells = <1>;
  94       #power-domain-cells = <1>;
  95       power-domains = <&rpmhpd SM8450_MMCX>;
  96       required-opps = <&rpmhpd_opp_low_svs>;
  97     };
  98 ...