Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Camera Clock & Reset Controller on SM8450
   8
   9 maintainers:
  10   - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
  11
  12 description: |
  13   Qualcomm camera clock control module provides the clocks, resets and power
  14   domains on SM8450.
  15
  16   See also::
  17     include/dt-bindings/clock/qcom,sm8450-camcc.h
  18     include/dt-bindings/clock/qcom,sm8550-camcc.h
  19
  20 properties:
  21   compatible:
  22     enum:
  23       - qcom,sm8450-camcc
  24       - qcom,sm8550-camcc
  25
  26   clocks:
  27     items:
  28       - description: Camera AHB clock from GCC
  29       - description: Board XO source
  30       - description: Board active XO source
  31       - description: Sleep clock source
  32
  33   power-domains:
  34     maxItems: 1
  35     description:
  36       A phandle and PM domain specifier for the MMCX power domain.
  37
  38   required-opps:
  39     maxItems: 1
  40     description:
  41       A phandle to an OPP node describing required MMCX performance point.
  42
  43   '#clock-cells':
  44     const: 1
  45
  46   '#reset-cells':
  47     const: 1
  48
  49   '#power-domain-cells':
  50     const: 1
  51
  52   reg:
  53     maxItems: 1
  54
  55 required:
  56   - compatible
  57   - reg
  58   - clocks
  59   - power-domains
  60   - required-opps
  61   - '#clock-cells'
  62   - '#reset-cells'
  63   - '#power-domain-cells'
  64
  65 additionalProperties: false
  66
  67 examples:
  68   - |
  69     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
  70     #include <dt-bindings/clock/qcom,rpmh.h>
  71     #include <dt-bindings/power/qcom,rpmhpd.h>
  72     clock-controller@ade0000 {
  73       compatible = "qcom,sm8450-camcc";
  74       reg = <0xade0000 0x20000>;
  75       clocks = <&gcc GCC_CAMERA_AHB_CLK>,
  76                <&rpmhcc RPMH_CXO_CLK>,
  77                <&rpmhcc RPMH_CXO_CLK_A>,
  78                <&sleep_clk>;
  79       power-domains = <&rpmhpd RPMHPD_MMCX>;
  80       required-opps = <&rpmhpd_opp_low_svs>;
  81       #clock-cells = <1>;
  82       #reset-cells = <1>;
  83       #power-domain-cells = <1>;
  84     };
  85 ...