1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350 Video Clock & Reset Controller
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm video clock control module provides the clocks, resets and power
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,videocc-sm8350.h
18 include/dt-bindings/reset/qcom,videocc-sm8350.h
23 - qcom,sc8280xp-videocc
28 - description: Board XO source
29 - description: Board active XO source
30 - description: Board sleep clock
34 A phandle and PM domain specifier for the MMCX power domain.
39 A phandle to an OPP node describing required MMCX performance point.
49 - $ref: qcom,gcc.yaml#
51 unevaluatedProperties: false
55 #include <dt-bindings/clock/qcom,rpmh.h>
56 #include <dt-bindings/power/qcom,rpmhpd.h>
58 clock-controller@abf0000 {
59 compatible = "qcom,sm8350-videocc";
60 reg = <0x0abf0000 0x10000>;
61 clocks = <&rpmhcc RPMH_CXO_CLK>,
62 <&rpmhcc RPMH_CXO_CLK_A>,
64 power-domains = <&rpmhpd RPMHPD_MMCX>;
65 required-opps = <&rpmhpd_opp_low_svs>;
68 #power-domain-cells = <1>;