1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM6375
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm graphics clock control module provides clocks, resets and power
14 domains on Qualcomm SoCs.
16 See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
25 - description: Board XO source
26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
28 - description: SNoC DVM GFX source
32 A phandle and PM domain specifier for the VDD_GX power rail
37 A phandle to an OPP node describing required VDD_GX performance point.
47 - $ref: qcom,gcc.yaml#
49 unevaluatedProperties: false
53 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
54 #include <dt-bindings/clock/qcom,rpmcc.h>
55 #include <dt-bindings/power/qcom-rpmpd.h>
61 clock-controller@5990000 {
62 compatible = "qcom,sm6375-gpucc";
63 reg = <0 0x05990000 0 0x9000>;
64 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
65 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
66 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
67 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
68 power-domains = <&rpmpd SM6375_VDDGX>;
69 required-opps = <&rpmpd_opp_low_svs>;
72 #power-domain-cells = <1>;