Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Graphics Clock & Reset Controller on SM6375
   8
   9 maintainers:
  10   - Konrad Dybcio <konrad.dybcio@linaro.org>
  11
  12 description: |
  13   Qualcomm graphics clock control module provides clocks, resets and power
  14   domains on Qualcomm SoCs.
  15
  16   See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
  17
  18 properties:
  19   compatible:
  20     enum:
  21       - qcom,sm6375-gpucc
  22
  23   clocks:
  24     items:
  25       - description: Board XO source
  26       - description: GPLL0 main branch source
  27       - description: GPLL0 div branch source
  28       - description: SNoC DVM GFX source
  29
  30   power-domains:
  31     description:
  32       A phandle and PM domain specifier for the VDD_GX power rail
  33     maxItems: 1
  34
  35   required-opps:
  36     description:
  37       A phandle to an OPP node describing required VDD_GX performance point.
  38     maxItems: 1
  39
  40 required:
  41   - compatible
  42   - clocks
  43   - power-domains
  44   - required-opps
  45
  46 allOf:
  47   - $ref: qcom,gcc.yaml#
  48
  49 unevaluatedProperties: false
  50
  51 examples:
  52   - |
  53     #include <dt-bindings/clock/qcom,sm6375-gcc.h>
  54     #include <dt-bindings/clock/qcom,rpmcc.h>
  55     #include <dt-bindings/power/qcom-rpmpd.h>
  56
  57     soc {
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         clock-controller@5990000 {
  62             compatible = "qcom,sm6375-gpucc";
  63             reg = <0 0x05990000 0 0x9000>;
  64             clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
  65                      <&gcc GCC_GPU_GPLL0_CLK_SRC>,
  66                      <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
  67                      <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
  68             power-domains = <&rpmpd SM6375_VDDGX>;
  69             required-opps = <&rpmpd_opp_low_svs>;
  70             #clock-cells = <1>;
  71             #reset-cells = <1>;
  72             #power-domain-cells = <1>;
  73         };
  74     };
  75 ...