Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Graphics Clock & Reset Controller on SM6125
   8
   9 maintainers:
  10   - Konrad Dybcio <konrad.dybcio@linaro.org>
  11
  12 description: |
  13   Qualcomm graphics clock control module provides clocks and power domains on
  14   Qualcomm SoCs.
  15
  16   See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
  17
  18 properties:
  19   compatible:
  20     enum:
  21       - qcom,sm6125-gpucc
  22
  23   clocks:
  24     items:
  25       - description: Board XO source
  26       - description: GPLL0 main branch source
  27
  28   '#clock-cells':
  29     const: 1
  30
  31   '#power-domain-cells':
  32     const: 1
  33
  34   reg:
  35     maxItems: 1
  36
  37 required:
  38   - compatible
  39   - reg
  40   - clocks
  41   - '#clock-cells'
  42   - '#power-domain-cells'
  43
  44 additionalProperties: false
  45
  46 examples:
  47   - |
  48     #include <dt-bindings/clock/qcom,gcc-sm6125.h>
  49     #include <dt-bindings/clock/qcom,rpmcc.h>
  50
  51     soc {
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         clock-controller@5990000 {
  56             compatible = "qcom,sm6125-gpucc";
  57             reg = <0x05990000 0x9000>;
  58             clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
  59                      <&gcc GCC_GPU_GPLL0_CLK_SRC>;
  60             #clock-cells = <1>;
  61             #power-domain-cells = <1>;
  62         };
  63     };
  64 ...