Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display Clock Controller for SM6115
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description: |
  13   Qualcomm display clock control module which supports the clocks and
  14   power domains on SM6115.
  15
  16   See also:
  17     include/dt-bindings/clock/qcom,sm6115-dispcc.h
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - qcom,sm6115-dispcc
  23
  24   clocks:
  25     items:
  26       - description: Board XO source
  27       - description: Board sleep clock
  28       - description: Byte clock from DSI PHY0
  29       - description: Pixel clock from DSI PHY0
  30       - description: GPLL0 DISP DIV clock from GCC
  31
  32   '#clock-cells':
  33     const: 1
  34
  35   '#reset-cells':
  36     const: 1
  37
  38   '#power-domain-cells':
  39     const: 1
  40
  41   reg:
  42     maxItems: 1
  43
  44 required:
  45   - compatible
  46   - reg
  47   - clocks
  48   - '#clock-cells'
  49   - '#reset-cells'
  50   - '#power-domain-cells'
  51
  52 additionalProperties: false
  53
  54 examples:
  55   - |
  56     #include <dt-bindings/clock/qcom,rpmcc.h>
  57     #include <dt-bindings/clock/qcom,gcc-sm6115.h>
  58     clock-controller@5f00000 {
  59       compatible = "qcom,sm6115-dispcc";
  60       reg = <0x5f00000 0x20000>;
  61       clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
  62                <&sleep_clk>,
  63                <&dsi0_phy 0>,
  64                <&dsi0_phy 1>,
  65                <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
  66       #clock-cells = <1>;
  67       #reset-cells = <1>;
  68       #power-domain-cells = <1>;
  69     };
  70 ...