1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
10 - Loic Poulain <loic.poulain@linaro.org>
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains on qcm2290.
16 See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
20 const: qcom,qcm2290-dispcc
24 - description: Board XO source
25 - description: Board active-only XO source
26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
28 - description: Byte clock from DSI PHY
29 - description: Pixel clock from DSI PHY
35 - const: gcc_disp_gpll0_clk_src
36 - const: gcc_disp_gpll0_div_clk_src
37 - const: dsi0_phy_pll_out_byteclk
38 - const: dsi0_phy_pll_out_dsiclk
46 '#power-domain-cells':
59 - '#power-domain-cells'
61 additionalProperties: false
65 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
66 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
67 #include <dt-bindings/clock/qcom,rpmcc.h>
68 clock-controller@5f00000 {
69 compatible = "qcom,qcm2290-dispcc";
70 reg = <0x5f00000 0x20000>;
71 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
72 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
73 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
74 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
77 clock-names = "bi_tcxo",
79 "gcc_disp_gpll0_clk_src",
80 "gcc_disp_gpll0_div_clk_src",
81 "dsi0_phy_pll_out_byteclk",
82 "dsi0_phy_pll_out_dsiclk";
85 #power-domain-cells = <1>;