1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm multimedia clock control module provides the clocks, resets and
47 '#power-domain-cells':
55 Protected clock specifier list as per common clock binding
59 Regulator supply for the GPU_GX GDSC
66 - '#power-domain-cells'
68 additionalProperties: false
82 - description: Board PXO source
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
86 - description: DSI phy instance 1 byte clock
87 - description: DSI phy instance 2 dsi clock
88 - description: DSI phy instance 2 byte clock
89 - description: HDMI phy PLL clock
112 - description: Board XO source
113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
115 - description: GPLL1 voted clock
116 - description: GFX3D clock source
117 - description: DSI phy instance 0 dsi clock
118 - description: DSI phy instance 0 byte clock
123 - const: mmss_gpll0_vote
126 - const: gfx3d_clk_src
140 - description: Board XO source
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
143 - description: GPLL1 voted clock
144 - description: GFX3D clock source
145 - description: DSI phy instance 0 dsi clock
146 - description: DSI phy instance 0 byte clock
147 - description: DSI phy instance 1 dsi clock
148 - description: DSI phy instance 1 byte clock
149 - description: HDMI phy PLL clock
150 - description: eDP phy PLL link clock
151 - description: eDP phy PLL vco clock
156 - const: mmss_gpll0_vote
159 - const: gfx3d_clk_src
165 - const: edp_link_clk
178 - description: Board XO source
179 - description: Board sleep source
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
183 - description: GPLL1 clock
184 - description: DSI phy instance 0 dsi clock
185 - description: DSI phy instance 0 byte clock
186 - description: DSI phy instance 1 dsi clock
187 - description: DSI phy instance 1 byte clock
188 - description: HDMI phy PLL clock
189 - description: eDP phy PLL link clock
190 - description: eDP phy PLL vco clock
196 - const: mmss_gpll0_vote
205 - const: edp_link_clk
226 const: qcom,mmcc-msm8994
231 - description: Board XO source
232 - description: Global PLL 0 clock
233 - description: MMSS NoC AHB clock
234 - description: GFX3D clock
235 - description: DSI phy instance 0 dsi clock
236 - description: DSI phy instance 0 byte clock
237 - description: DSI phy instance 1 dsi clock
238 - description: DSI phy instance 1 byte clock
239 - description: HDMI phy PLL clock
246 - const: oxili_gfx3d_clk_src
257 const: qcom,mmcc-msm8996
262 - description: Board XO source
263 - description: Global PLL 0 clock
264 - description: MMSS NoC AHB clock
265 - description: DSI phy instance 0 dsi clock
266 - description: DSI phy instance 0 byte clock
267 - description: DSI phy instance 1 dsi clock
268 - description: DSI phy instance 1 byte clock
269 - description: HDMI phy PLL clock
275 - const: gcc_mmss_noc_cfg_ahb_clk
286 const: qcom,mmcc-msm8998
291 - description: Board XO source
292 - description: Global PLL 0 clock
293 - description: DSI phy instance 0 dsi clock
294 - description: DSI phy instance 0 byte clock
295 - description: DSI phy instance 1 dsi clock
296 - description: DSI phy instance 1 byte clock
297 - description: HDMI phy PLL clock
298 - description: DisplayPort phy PLL link clock
299 - description: DisplayPort phy PLL vco clock
300 - description: Global PLL 0 DIV clock
326 - description: Board XO source
327 - description: Board sleep source
328 - description: Global PLL 0 clock
329 - description: Global PLL 0 DIV clock
330 - description: DSI phy instance 0 dsi clock
331 - description: DSI phy instance 0 byte clock
332 - description: DSI phy instance 1 dsi clock
333 - description: DSI phy instance 1 byte clock
334 - description: DisplayPort phy PLL link clock
335 - description: DisplayPort phy PLL vco clock
347 - const: dp_link_2x_clk_divsel_five
348 - const: dp_vco_divided_clk_src_mux
351 # Example for MMCC for MSM8960:
353 clock-controller@4000000 {
354 compatible = "qcom,mmcc-msm8960";
355 reg = <0x4000000 0x1000>;
358 #power-domain-cells = <1>;