1 High-Frequency PLL (HFPLL)
8 shall contain only one of the following. The generic
9 compatible "qcom,hfpll" should be also included.
11 "qcom,hfpll-ipq8064", "qcom,hfpll"
12 "qcom,hfpll-apq8064", "qcom,hfpll"
13 "qcom,hfpll-msm8974", "qcom,hfpll"
14 "qcom,hfpll-msm8960", "qcom,hfpll"
15 "qcom,msm8976-hfpll-a53", "qcom,hfpll"
16 "qcom,msm8976-hfpll-a72", "qcom,hfpll"
17 "qcom,msm8976-hfpll-cci", "qcom,hfpll"
21 Value type: <prop-encoded-array>
22 Definition: address and size of HPLL registers. An optional second
23 element specifies the address and size of the alias
28 Value type: <prop-encoded-array>
29 Definition: reference to the xo clock.
33 Value type: <stringlist>
34 Definition: must be "xo".
39 Definition: Name of the PLL. Typically hfpllX where X is a CPU number
40 starting at 0. Otherwise hfpll_Y where Y is more specific
45 1) An HFPLL for the L2 cache.
47 clock-controller@f9016000 {
48 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
49 reg = <0xf9016000 0x30>;
52 clock-output-names = "hfpll_l2";
55 2) An HFPLL for CPU0. This HFPLL has the alias register region.
57 clock-controller@f908a000 {
58 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
59 reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
62 clock-output-names = "hfpll0";