1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm graphics clock control module provides the clocks, resets and power
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,gpucc-sdm845.h
18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h
19 include/dt-bindings/clock/qcom,gpucc-sc7180.h
20 include/dt-bindings/clock/qcom,gpucc-sc7280.h
21 include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
22 include/dt-bindings/clock/qcom,gpucc-sm6350.h
23 include/dt-bindings/clock/qcom,gpucc-sm8150.h
24 include/dt-bindings/clock/qcom,gpucc-sm8250.h
25 include/dt-bindings/clock/qcom,gpucc-sm8350.h
43 - description: Board XO source
44 - description: GPLL0 main branch source
45 - description: GPLL0 div branch source
50 - const: gcc_gpu_gpll0_clk_src
51 - const: gcc_gpu_gpll0_div_clk_src
62 '#power-domain-cells':
75 - '#power-domain-cells'
77 additionalProperties: false
81 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
82 #include <dt-bindings/clock/qcom,rpmh.h>
83 clock-controller@5090000 {
84 compatible = "qcom,sdm845-gpucc";
85 reg = <0x05090000 0x9000>;
86 clocks = <&rpmhcc RPMH_CXO_CLK>,
87 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
88 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
89 clock-names = "bi_tcxo",
90 "gcc_gpu_gpll0_clk_src",
91 "gcc_gpu_gpll0_div_clk_src";
94 #power-domain-cells = <1>;