Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Graphics Clock & Reset Controller Binding
   8
   9 maintainers:
  10   - Robert Foss <robert.foss@linaro.org>
  11
  12 description: |
  13   Qualcomm graphics clock control module which supports the clocks, resets and
  14   power domains on Qualcomm SoCs.
  15
  16   See also:
  17     dt-bindings/clock/qcom,gpucc-sm8350.h
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - qcom,sm8350-gpucc
  23
  24   clocks:
  25     items:
  26       - description: Board XO source
  27       - description: GPLL0 main branch source
  28       - description: GPLL0 div branch source
  29
  30   '#clock-cells':
  31     const: 1
  32
  33   '#reset-cells':
  34     const: 1
  35
  36   '#power-domain-cells':
  37     const: 1
  38
  39   reg:
  40     maxItems: 1
  41
  42 required:
  43   - compatible
  44   - reg
  45   - clocks
  46   - '#clock-cells'
  47   - '#reset-cells'
  48   - '#power-domain-cells'
  49
  50 additionalProperties: false
  51
  52 examples:
  53   - |
  54     #include <dt-bindings/clock/qcom,gcc-sm8350.h>
  55     #include <dt-bindings/clock/qcom,rpmh.h>
  56
  57     soc {
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         clock-controller@3d90000 {
  62             compatible = "qcom,sm8350-gpucc";
  63             reg = <0 0x03d90000 0 0x9000>;
  64             clocks = <&rpmhcc RPMH_CXO_CLK>,
  65                      <&gcc GCC_GPU_GPLL0_CLK_SRC>,
  66                      <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
  67             #clock-cells = <1>;
  68             #reset-cells = <1>;
  69             #power-domain-cells = <1>;
  70         };
  71     };
  72 ...