1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SDX65
10 - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
13 Qualcomm global clock control module which supports the clocks, resets and
14 power domains on SDX65
17 - dt-bindings/clock/qcom,gcc-sdx65.h
28 - description: Board XO source
29 - description: Board active XO source
30 - description: Sleep clock source
31 - description: PCIE Pipe clock source
32 - description: USB3 phy wrapper pipe clock source
33 - description: PLL test clock source (Optional clock)
41 - const: pcie_pipe_clk
42 - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
43 - const: core_bi_pll_test_se # Optional clock
52 '#power-domain-cells':
62 - '#power-domain-cells'
64 additionalProperties: false
68 #include <dt-bindings/clock/qcom,rpmh.h>
69 clock-controller@100000 {
70 compatible = "qcom,gcc-sdx65";
71 reg = <0x100000 0x1f7400>;
72 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
73 <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
74 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
75 "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
78 #power-domain-cells = <1>;