Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Global Clock & Reset Controller Binding for SC7280
   8
   9 maintainers:
  10   - Taniya Das <tdas@codeaurora.org>
  11
  12 description: |
  13   Qualcomm global clock control module which supports the clocks, resets and
  14   power domains on SC7280.
  15
  16   See also:
  17   - dt-bindings/clock/qcom,gcc-sc7280.h
  18
  19 properties:
  20   compatible:
  21     const: qcom,gcc-sc7280
  22
  23   clocks:
  24     items:
  25       - description: Board XO source
  26       - description: Board active XO source
  27       - description: Sleep clock source
  28       - description: PCIE-0 pipe clock source
  29       - description: PCIE-1 pipe clock source
  30       - description: USF phy rx symbol 0 clock source
  31       - description: USF phy rx symbol 1 clock source
  32       - description: USF phy tx symbol 0 clock source
  33       - description: USB30 phy wrapper pipe clock source
  34
  35   clock-names:
  36     items:
  37       - const: bi_tcxo
  38       - const: bi_tcxo_ao
  39       - const: sleep_clk
  40       - const: pcie_0_pipe_clk
  41       - const: pcie_1_pipe_clk
  42       - const: ufs_phy_rx_symbol_0_clk
  43       - const: ufs_phy_rx_symbol_1_clk
  44       - const: ufs_phy_tx_symbol_0_clk
  45       - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
  46
  47 required:
  48   - compatible
  49   - clocks
  50   - clock-names
  51
  52 allOf:
  53   - $ref: qcom,gcc.yaml#
  54
  55 unevaluatedProperties: false
  56
  57 examples:
  58   - |
  59     #include <dt-bindings/clock/qcom,rpmh.h>
  60     clock-controller@100000 {
  61       compatible = "qcom,gcc-sc7280";
  62       reg = <0x00100000 0x1f0000>;
  63       clocks = <&rpmhcc RPMH_CXO_CLK>,
  64                <&rpmhcc RPMH_CXO_CLK_A>,
  65                <&sleep_clk>,
  66                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
  67                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
  68                <&ufs_phy_tx_symbol_0_clk>,
  69                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
  70
  71       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
  72                      "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
  73                      "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
  74                      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
  75       #clock-cells = <1>;
  76       #reset-cells = <1>;
  77       #power-domain-cells = <1>;
  78     };
  79 ...