Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Global Clock & Reset Controller on SC7280
   8
   9 maintainers:
  10   - Taniya Das <quic_tdas@quicinc.com>
  11
  12 description: |
  13   Qualcomm global clock control module provides the clocks, resets and power
  14   domains on SC7280.
  15
  16   See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
  17
  18 properties:
  19   compatible:
  20     const: qcom,gcc-sc7280
  21
  22   clocks:
  23     items:
  24       - description: Board XO source
  25       - description: Board active XO source
  26       - description: Sleep clock source
  27       - description: PCIE-0 pipe clock source
  28       - description: PCIE-1 pipe clock source
  29       - description: USF phy rx symbol 0 clock source
  30       - description: USF phy rx symbol 1 clock source
  31       - description: USF phy tx symbol 0 clock source
  32       - description: USB30 phy wrapper pipe clock source
  33
  34   clock-names:
  35     items:
  36       - const: bi_tcxo
  37       - const: bi_tcxo_ao
  38       - const: sleep_clk
  39       - const: pcie_0_pipe_clk
  40       - const: pcie_1_pipe_clk
  41       - const: ufs_phy_rx_symbol_0_clk
  42       - const: ufs_phy_rx_symbol_1_clk
  43       - const: ufs_phy_tx_symbol_0_clk
  44       - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
  45
  46   power-domains:
  47     items:
  48       - description: CX domain
  49
  50 required:
  51   - compatible
  52   - clocks
  53   - clock-names
  54
  55 allOf:
  56   - $ref: qcom,gcc.yaml#
  57
  58 unevaluatedProperties: false
  59
  60 examples:
  61   - |
  62     #include <dt-bindings/clock/qcom,rpmh.h>
  63     #include <dt-bindings/power/qcom-rpmpd.h>
  64
  65     clock-controller@100000 {
  66       compatible = "qcom,gcc-sc7280";
  67       reg = <0x00100000 0x1f0000>;
  68       clocks = <&rpmhcc RPMH_CXO_CLK>,
  69                <&rpmhcc RPMH_CXO_CLK_A>,
  70                <&sleep_clk>,
  71                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
  72                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
  73                <&ufs_phy_tx_symbol_0_clk>,
  74                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
  75
  76       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
  77                      "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
  78                      "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
  79                      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
  80       power-domains = <&rpmhpd SC7280_CX>;
  81       #clock-cells = <1>;
  82       #reset-cells = <1>;
  83       #power-domain-cells = <1>;
  84     };
  85 ...