1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
10 - Jonathan Marek <jonathan@marek.ca>
13 Qualcomm display clock control module provides the clocks, resets and power
14 domains on SM8150/SM8250/SM8350.
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
31 - description: Board XO source
32 - description: Byte clock from DSI PHY0
33 - description: Pixel clock from DSI PHY0
34 - description: Byte clock from DSI PHY1
35 - description: Pixel clock from DSI PHY1
36 - description: Link clock from DP PHY
37 - description: VCO DIV clock from DP PHY
42 - const: dsi0_phy_pll_out_byteclk
43 - const: dsi0_phy_pll_out_dsiclk
44 - const: dsi1_phy_pll_out_byteclk
45 - const: dsi1_phy_pll_out_dsiclk
46 - const: dp_phy_pll_link_clk
47 - const: dp_phy_pll_vco_div_clk
55 '#power-domain-cells':
63 A phandle and PM domain specifier for the MMCX power domain.
68 A phandle to an OPP node describing required MMCX performance point.
78 - '#power-domain-cells'
80 additionalProperties: false
84 #include <dt-bindings/clock/qcom,rpmh.h>
85 #include <dt-bindings/power/qcom,rpmhpd.h>
86 clock-controller@af00000 {
87 compatible = "qcom,sm8250-dispcc";
88 reg = <0x0af00000 0x10000>;
89 clocks = <&rpmhcc RPMH_CXO_CLK>,
96 clock-names = "bi_tcxo",
97 "dsi0_phy_pll_out_byteclk",
98 "dsi0_phy_pll_out_dsiclk",
99 "dsi1_phy_pll_out_byteclk",
100 "dsi1_phy_pll_out_dsiclk",
101 "dp_phy_pll_link_clk",
102 "dp_phy_pll_vco_div_clk";
105 #power-domain-cells = <1>;
106 power-domains = <&rpmhpd RPMHPD_MMCX>;
107 required-opps = <&rpmhpd_opp_low_svs>;