1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
10 - Jonathan Marek <jonathan@marek.ca>
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains on SM8150 and SM8250.
17 dt-bindings/clock/qcom,dispcc-sm8150.h
18 dt-bindings/clock/qcom,dispcc-sm8250.h
29 - description: Board XO source
30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
34 - description: Link clock from DP PHY
35 - description: VCO DIV clock from DP PHY
40 - const: dsi0_phy_pll_out_byteclk
41 - const: dsi0_phy_pll_out_dsiclk
42 - const: dsi1_phy_pll_out_byteclk
43 - const: dsi1_phy_pll_out_dsiclk
44 - const: dp_phy_pll_link_clk
45 - const: dp_phy_pll_vco_div_clk
53 '#power-domain-cells':
61 A phandle and PM domain specifier for the MMCX power domain.
66 A phandle to an OPP node describing required MMCX performance point.
76 - '#power-domain-cells'
78 additionalProperties: false
82 #include <dt-bindings/clock/qcom,rpmh.h>
83 #include <dt-bindings/power/qcom-rpmpd.h>
84 clock-controller@af00000 {
85 compatible = "qcom,sm8250-dispcc";
86 reg = <0x0af00000 0x10000>;
87 clocks = <&rpmhcc RPMH_CXO_CLK>,
94 clock-names = "bi_tcxo",
95 "dsi0_phy_pll_out_byteclk",
96 "dsi0_phy_pll_out_dsiclk",
97 "dsi1_phy_pll_out_byteclk",
98 "dsi1_phy_pll_out_dsiclk",
99 "dp_phy_pll_link_clk",
100 "dp_phy_pll_vco_div_clk";
103 #power-domain-cells = <1>;
104 power-domains = <&rpmhpd SM8250_MMCX>;
105 required-opps = <&rpmhpd_opp_low_svs>;