1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM6350
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
13 Qualcomm display clock control module provides the clocks, resets and power
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
20 const: qcom,sm6350-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
27 - description: Pixel clock from DSI PHY
28 - description: Link clock from DP PHY
29 - description: VCO DIV clock from DP PHY
34 - const: gcc_disp_gpll0_clk
35 - const: dsi0_phy_pll_out_byteclk
36 - const: dsi0_phy_pll_out_dsiclk
37 - const: dp_phy_pll_link_clk
38 - const: dp_phy_pll_vco_div_clk
46 '#power-domain-cells':
59 - '#power-domain-cells'
61 additionalProperties: false
65 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
66 #include <dt-bindings/clock/qcom,rpmh.h>
67 clock-controller@af00000 {
68 compatible = "qcom,sm6350-dispcc";
69 reg = <0x0af00000 0x20000>;
70 clocks = <&rpmhcc RPMH_CXO_CLK>,
71 <&gcc GCC_DISP_GPLL0_CLK>,
76 clock-names = "bi_tcxo",
78 "dsi0_phy_pll_out_byteclk",
79 "dsi0_phy_pll_out_dsiclk",
80 "dp_phy_pll_link_clk",
81 "dp_phy_pll_vco_div_clk";
84 #power-domain-cells = <1>;