1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC8280XP
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains for the two MDSS instances on SC8280XP.
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
22 - qcom,sc8280xp-dispcc0
23 - qcom,sc8280xp-dispcc1
27 - description: AHB interface clock,
28 - description: SoC CXO clock
29 - description: SoC sleep clock
30 - description: DisplayPort 0 link clock
31 - description: DisplayPort 0 VCO div clock
32 - description: DisplayPort 1 link clock
33 - description: DisplayPort 1 VCO div clock
34 - description: DisplayPort 2 link clock
35 - description: DisplayPort 2 VCO div clock
36 - description: DisplayPort 3 link clock
37 - description: DisplayPort 3 VCO div clock
38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
40 - description: DSI 1 PLL byte clock
41 - description: DSI 1 PLL DSI clock
49 '#power-domain-cells':
57 - description: MMCX power domain
65 - '#power-domain-cells'
67 additionalProperties: false
71 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
72 #include <dt-bindings/clock/qcom,rpmh.h>
73 #include <dt-bindings/power/qcom-rpmpd.h>
74 clock-controller@af00000 {
75 compatible = "qcom,sc8280xp-dispcc0";
76 reg = <0x0af00000 0x20000>;
77 clocks = <&gcc GCC_DISP_AHB_CLK>,
78 <&rpmhcc RPMH_CXO_CLK>,
92 power-domains = <&rpmhpd SC8280XP_MMCX>;
95 #power-domain-cells = <1>;