1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35D1 Clock Controller Module
10 - Chi-Fang Li <cfli0@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
14 The MA35D1 clock controller generates clocks for the whole chip,
15 including system clocks and all peripheral clocks.
18 include/dt-bindings/clock/ma35d1-clk.h
23 - const: nuvoton,ma35d1-clk
36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
37 EPLL, and VPLL in sequential.
44 $ref: /schemas/types.yaml#/definitions/non-unique-string-array
52 additionalProperties: false
57 clock-controller@40460200 {
58 compatible = "nuvoton,ma35d1-clk";
59 reg = <0x40460200 0x100>;