1 * Gated Clock bindings for Marvell EBU SoCs
3 Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
4 peripheral clocks to be gated to save some power. The clock consumer
5 should specify the desired clock by having the clock ID in its
6 "clocks" phandle cell. The clock ID is directly mapped to the
7 corresponding clock gating control bit in HW to ease manual clock
10 The following is a list of provided IDs for Armada 370:
12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
16 3 ge1 Gigabit Ethernet 1
17 4 ge0 Gigabit Ethernet 0
22 23 crypto CESA (crypto engine)
23 25 tdm Time Division Mplx
27 The following is a list of provided IDs for Armada 375:
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
36 11 nd_clk Nand Flash Cntrl
37 14 sata0_link SATA 0 Link
38 15 sata0_core SATA 0 Core
42 19 gop Gigabit Ethernet MAC
43 20 sata1_link SATA 1 Link
44 21 sata1_core SATA 1 Core
48 25 tdm Time Division Mplx
49 28 crypto0_enc Cryptographic Unit Port 0 Encryption
50 29 crypto0_core Cryptographic Unit Port 0 Core
51 30 crypto1_enc Cryptographic Unit Port 1 Encryption
52 31 crypto1_core Cryptographic Unit Port 1 Core
54 The following is a list of provided IDs for Armada 380/385:
56 -----------------------------------
58 2 ge2 Gigabit Ethernet 2
59 3 ge1 Gigabit Ethernet 1
60 4 ge0 Gigabit Ethernet 0
68 13 bm Buffer Management
69 14 crypto0z Cryptographic 0 Z
71 16 crypto1z Cryptographic 1 Z
74 21 crypto1 Cryptographic 1
76 23 crypto0 Cryptographic 0
77 25 tdm Time Division Multiplexing
81 The following is a list of provided IDs for Armada 39x:
83 -----------------------------------
95 The following is a list of provided IDs for Armada XP:
97 -----------------------------------
99 1 ge3 Gigabit Ethernet 3
100 2 ge2 Gigabit Ethernet 2
101 3 ge1 Gigabit Ethernet 1
102 4 ge0 Gigabit Ethernet 0
116 23 crypto CESA engine
117 25 tdm Time Division Mplx
122 The following is a list of provided IDs for 98dx3236:
124 -----------------------------------
125 3 ge1 Gigabit Ethernet 1
126 4 ge0 Gigabit Ethernet 0
132 The following is a list of provided IDs for Dove:
134 -----------------------------------
137 2 ge Gigabit Ethernet
144 11 camera Camera Cntrl
147 15 crypto CESA engine
149 22 pdma Peripheral DMA
152 30 gephy Gigabit Ethernel PHY
153 Note: gephy(30) is implemented as a parent clock of ge(2)
155 The following is a list of provided IDs for Kirkwood:
157 -----------------------------------
158 0 ge0 Gigabit Ethernet 0
162 5 tsu Transp. Stream Unit
170 17 crypto CESA engine
172 19 ge1 Gigabit Ethernet 1
173 20 tdm Time Division Mplx
176 - compatible : shall be one of the following:
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 compatible = "marvell,dove-gating-clock";
196 /* default parent clock is tclk */
197 clocks = <&core_clk 0>;
202 compatible = "marvell,dove-sdhci";
203 /* get clk gate bit 8 (sdio0) */
204 clocks = <&gate_clk 8>;