1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN966X Generic Clock Controller
10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
13 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
14 ddr_clk and sys_clk. This clock controller generates and supplies
15 clock to various peripherals within the SoC.
19 const: microchip,lan966x-gck
24 - description: Generic clock registers
25 - description: Optional gate clock registers
29 - description: CPU clock source
30 - description: DDR clock source
31 - description: System clock source
49 additionalProperties: false
53 clks: clock-controller@e00c00a8 {
54 compatible = "microchip,lan966x-gck";
56 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
57 clock-names = "cpu", "ddr", "sys";
58 reg = <0xe00c00a8 0x38>;