1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MTMIPS SoCs System Controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MIPS and Ralink SoCs provides a system controller to allow
14 to access to system control registers. These registers include clock
15 and reset related ones so this node is both clock and reset provider
16 for the rest of the world.
18 These SoCs have an XTAL from where the cpu clock is
19 provided as well as derived clocks for the bus and the peripherals.
41 The first cell indicates the clock number.
46 The first cell indicates the reset bit within the register.
55 additionalProperties: false
60 compatible = "ralink,rt5350-sysc", "syscon";