1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT6795
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 The clock architecture in MediaTek like below
21 The devices provide clock gate control in different IP blocks.
26 - mediatek,mt6795-mfgcfg
27 - mediatek,mt6795-vdecsys
28 - mediatek,mt6795-vencsys
41 additionalProperties: false
49 mfgcfg: clock-controller@13000000 {
50 compatible = "mediatek,mt6795-mfgcfg";
51 reg = <0 0x13000000 0 0x1000>;
55 vdecsys: clock-controller@16000000 {
56 compatible = "mediatek,mt6795-vdecsys";
57 reg = <0 0x16000000 0 0x1000>;
61 vencsys: clock-controller@18000000 {
62 compatible = "mediatek,mt6795-vencsys";
63 reg = <0 0x18000000 0 0x1000>;