Documentation/devicetree/bindings/clock/lpc1850-ccu.txt

   1 * NXP LPC1850 Clock Control Unit (CCU)
   2
   3 Each CGU base clock has several clock branches which can be turned on
   4 or off independently by the Clock Control Units CCU1 or CCU2. The
   5 branch clocks are distributed between CCU1 and CCU2.
   6
   7  - Above text taken from NXP LPC1850 User Manual.
   8
   9 This binding uses the common clock binding:
  10     Documentation/devicetree/bindings/clock/clock-bindings.txt
  11
  12 Required properties:
  13 - compatible:
  14         Should be "nxp,lpc1850-ccu"
  15 - reg:
  16         Shall define the base and range of the address space
  17         containing clock control registers
  18 - #clock-cells:
  19         Shall have value <1>.  The permitted clock-specifier values
  20         are the branch clock names defined in table below.
  21 - clocks:
  22         Shall contain a list of phandles for the base clocks routed
  23         from the CGU to the specific CCU. See mapping of base clocks
  24         and CCU in table below.
  25 - clock-names:
  26         Shall contain a list of names for the base clock routed
  27         from the CGU to the specific CCU. Valid CCU clock names:
  28         "base_usb0_clk",  "base_periph_clk", "base_usb1_clk",
  29         "base_cpu_clk",   "base_spifi_clk",  "base_spi_clk",
  30         "base_apb1_clk",  "base_apb3_clk",   "base_adchs_clk",
  31         "base_sdio_clk",  "base_ssp0_clk",   "base_ssp1_clk",
  32         "base_uart0_clk", "base_uart1_clk",  "base_uart2_clk",
  33         "base_uart3_clk", "base_audio_clk"
  34
  35 Which branch clocks that are available on the CCU depends on the
  36 specific LPC part. Check the user manual for your specific part.
  37
  38 A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
  39
  40 Example board file:
  41
  42 soc {
  43         ccu1: clock-controller@40051000 {
  44                 compatible = "nxp,lpc1850-ccu";
  45                 reg = <0x40051000 0x1000>;
  46                 #clock-cells = <1>;
  47                 clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
  48                          <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
  49                          <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
  50                          <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
  51                 clock-names = "base_apb3_clk",   "base_apb1_clk",
  52                               "base_spifi_clk",  "base_cpu_clk",
  53                               "base_periph_clk", "base_usb0_clk",
  54                               "base_usb1_clk",   "base_spi_clk";
  55         };
  56
  57         ccu2: clock-controller@40052000 {
  58                 compatible = "nxp,lpc1850-ccu";
  59                 reg = <0x40052000 0x1000>;
  60                 #clock-cells = <1>;
  61                 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
  62                          <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
  63                          <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
  64                          <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
  65                 clock-names = "base_audio_clk", "base_uart3_clk",
  66                               "base_uart2_clk", "base_uart1_clk",
  67                               "base_uart0_clk", "base_ssp1_clk",
  68                               "base_ssp0_clk",  "base_sdio_clk";
  69         };
  70
  71         /* A user of CCU brach clocks */
  72         uart1: serial@40082000 {
  73                 ...
  74                 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
  75                 ...
  76         };
  77 };