1 Binding for IDT VersaClock 5,6 programmable i2c clock generators.
3 The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
4 generators providing from 3 to 12 output clocks.
9 - compatible: shall be one of
15 - reg: i2c device address, shall be 0x68 or 0x6a.
16 - #clock-cells: from common clock binding; shall be set to 1.
17 - clocks: from common clock binding; list of parent clock handles,
20 5p49v6901: (required) either or both of XTAL or CLKIN
23 - 5p49v5935: (optional) property not present (internal
24 Xtal used) or CLKIN reference
26 - clock-names: from common clock binding; clock input names, can be
29 5p49v6901: (required) either or both of "xin", "clkin".
31 - 5p49v5935: (optional) property not present or "clkin".
33 ==Mapping between clock specifier and physical pins==
35 When referencing the provided clock in the DT using phandle and
36 clock specifier, the following mapping applies:
65 /* 25MHz reference crystal */
67 compatible = "fixed-clock";
69 clock-frequency = <25000000>;
74 /* IDT 5P49V5923 i2c clock generator */
75 vc5: clock-generator@6a {
76 compatible = "idt,5p49v5923";
80 /* Connect XIN input to 25MHz reference */
86 /* Consumer referencing the 5P49V5923 pin OUT1 */