1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
4 to Audio Subsystem block available in the S5PV210 and compatible SoCs.
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
16 not specified (i.e. xusbxti is used for PLL reference), it is fixed to
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
19 - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
20 specified, it is fixed to a clock named "iiscdclk0".
21 - sclk_audio0: Audio bus clock, parent of mout_i2s.
23 - clock-names: Aliases for the above clocks. They should be "hclk",
24 "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
26 All available clocks are defined as preprocessor macros in
27 dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
30 Example: Clock controller node.
32 clk_audss: clock-controller@c0900000 {
33 compatible = "samsung,s5pv210-audss-clock";
34 reg = <0xc0900000 0x1000>;
36 clock-names = "hclk", "xxti",
37 "fout_epll", "sclk_audio0";
38 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
39 <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
42 Example: I2S controller node that consumes the clock generated by the clock
43 controller. Refer to the standard clock bindings for information
44 about 'clocks' and 'clock-names' property.
48 clock-names = "iis", "i2s_opclk0",
50 clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
51 <&clk_audss CLK_DOUT_AUD_BUS>;