1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
14 utilizes a programmable phase lock loop.
16 Link: https://www.cirrus.com/products/cs2000/
25 Common clock binding for CLK_IN, XTI/REF_CLK
39 cirrus,aux-output-source:
41 Specifies the function of the auxiliary clock output pin
42 $ref: /schemas/types.yaml#/definitions/uint32
44 - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
45 - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
46 - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
47 - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
52 This mode allows the PLL to maintain lock even when CLK_IN
53 has missing pulses for up to 20 ms.
54 $ref: /schemas/types.yaml#/definitions/flag
58 In dynamic mode, the CLK_IN input is used to drive the
59 digital PLL of the silicon.
60 If not given, the static mode shall be used to derive the
61 output signal directly from the REF_CLK input.
62 $ref: /schemas/types.yaml#/definitions/flag
71 additionalProperties: false
75 #include <dt-bindings/clock/cirrus,cs2000-cp.h>
84 compatible = "cirrus,cs2000-cp";
86 clocks = <&rcar_sound 0>, <&x12_clk>;
87 clock-names = "clk_in", "ref_clk";
88 cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;