Documentation/devicetree/bindings/cache/qcom,llcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Last Level Cache Controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description: |
  13   LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
  14   that can be shared by multiple clients. Clients here are different cores in the
  15   SoC, the idea is to minimize the local caches at the clients and migrate to
  16   common pool of memory. Cache memory is divided into partitions called slices
  17   which are assigned to clients. Clients can query the slice details, activate
  18   and deactivate them.
  19
  20 properties:
  21   compatible:
  22     enum:
  23       - qcom,qdu1000-llcc
  24       - qcom,sc7180-llcc
  25       - qcom,sc7280-llcc
  26       - qcom,sc8180x-llcc
  27       - qcom,sc8280xp-llcc
  28       - qcom,sdm845-llcc
  29       - qcom,sm6350-llcc
  30       - qcom,sm7150-llcc
  31       - qcom,sm8150-llcc
  32       - qcom,sm8250-llcc
  33       - qcom,sm8350-llcc
  34       - qcom,sm8450-llcc
  35       - qcom,sm8550-llcc
  36
  37   reg:
  38     minItems: 2
  39     maxItems: 9
  40
  41   reg-names:
  42     minItems: 2
  43     maxItems: 9
  44
  45   interrupts:
  46     maxItems: 1
  47
  48   nvmem-cells:
  49     items:
  50       - description: Reference to an nvmem node for multi channel DDR
  51
  52   nvmem-cell-names:
  53     items:
  54       - const: multi-chan-ddr
  55
  56 required:
  57   - compatible
  58   - reg
  59   - reg-names
  60
  61 allOf:
  62   - if:
  63       properties:
  64         compatible:
  65           contains:
  66             enum:
  67               - qcom,sc7180-llcc
  68               - qcom,sm6350-llcc
  69     then:
  70       properties:
  71         reg:
  72           items:
  73             - description: LLCC0 base register region
  74             - description: LLCC broadcast base register region
  75         reg-names:
  76           items:
  77             - const: llcc0_base
  78             - const: llcc_broadcast_base
  79
  80   - if:
  81       properties:
  82         compatible:
  83           contains:
  84             enum:
  85               - qcom,sc7280-llcc
  86     then:
  87       properties:
  88         reg:
  89           items:
  90             - description: LLCC0 base register region
  91             - description: LLCC1 base register region
  92             - description: LLCC broadcast base register region
  93         reg-names:
  94           items:
  95             - const: llcc0_base
  96             - const: llcc1_base
  97             - const: llcc_broadcast_base
  98
  99   - if:
 100       properties:
 101         compatible:
 102           contains:
 103             enum:
 104               - qcom,qdu1000-llcc
 105               - qcom,sc8180x-llcc
 106               - qcom,sc8280xp-llcc
 107     then:
 108       properties:
 109         reg:
 110           items:
 111             - description: LLCC0 base register region
 112             - description: LLCC1 base register region
 113             - description: LLCC2 base register region
 114             - description: LLCC3 base register region
 115             - description: LLCC4 base register region
 116             - description: LLCC5 base register region
 117             - description: LLCC6 base register region
 118             - description: LLCC7 base register region
 119             - description: LLCC broadcast base register region
 120         reg-names:
 121           items:
 122             - const: llcc0_base
 123             - const: llcc1_base
 124             - const: llcc2_base
 125             - const: llcc3_base
 126             - const: llcc4_base
 127             - const: llcc5_base
 128             - const: llcc6_base
 129             - const: llcc7_base
 130             - const: llcc_broadcast_base
 131
 132   - if:
 133       properties:
 134         compatible:
 135           contains:
 136             enum:
 137               - qcom,sdm845-llcc
 138               - qcom,sm8150-llcc
 139               - qcom,sm8250-llcc
 140               - qcom,sm8350-llcc
 141               - qcom,sm8450-llcc
 142               - qcom,sm8550-llcc
 143     then:
 144       properties:
 145         reg:
 146           items:
 147             - description: LLCC0 base register region
 148             - description: LLCC1 base register region
 149             - description: LLCC2 base register region
 150             - description: LLCC3 base register region
 151             - description: LLCC broadcast base register region
 152         reg-names:
 153           items:
 154             - const: llcc0_base
 155             - const: llcc1_base
 156             - const: llcc2_base
 157             - const: llcc3_base
 158             - const: llcc_broadcast_base
 159
 160 additionalProperties: false
 161
 162 examples:
 163   - |
 164     #include <dt-bindings/interrupt-controller/arm-gic.h>
 165
 166     soc {
 167         #address-cells = <2>;
 168         #size-cells = <2>;
 169
 170         system-cache-controller@1100000 {
 171             compatible = "qcom,sdm845-llcc";
 172             reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
 173                 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
 174                 <0 0x01300000 0 0x50000>;
 175             reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
 176                 "llcc3_base", "llcc_broadcast_base";
 177             interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 178         };
 179     };