1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Bjorn Andersson <andersson@kernel.org>
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
14 that can be shared by multiple clients. Clients here are different cores in the
15 SoC, the idea is to minimize the local caches at the clients and migrate to
16 common pool of memory. Cache memory is divided into partitions called slices
17 which are assigned to clients. Clients can query the slice details, activate
52 - description: Reference to an nvmem node for multi channel DDR
56 - const: multi-chan-ddr
76 - description: LLCC0 base register region
77 - description: LLCC broadcast base register region
81 - const: llcc_broadcast_base
93 - description: LLCC0 base register region
94 - description: LLCC1 base register region
95 - description: LLCC broadcast base register region
100 - const: llcc_broadcast_base
114 - description: LLCC0 base register region
115 - description: LLCC1 base register region
116 - description: LLCC2 base register region
117 - description: LLCC3 base register region
118 - description: LLCC4 base register region
119 - description: LLCC5 base register region
120 - description: LLCC6 base register region
121 - description: LLCC7 base register region
122 - description: LLCC broadcast base register region
133 - const: llcc_broadcast_base
150 - description: LLCC0 base register region
151 - description: LLCC1 base register region
152 - description: LLCC2 base register region
153 - description: LLCC3 base register region
154 - description: LLCC broadcast base register region
161 - const: llcc_broadcast_base
163 additionalProperties: false
167 #include <dt-bindings/interrupt-controller/arm-gic.h>
170 #address-cells = <2>;
173 system-cache-controller@1100000 {
174 compatible = "qcom,sdm845-llcc";
175 reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
176 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
177 <0 0x01300000 0 0x50000>;
178 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
179 "llcc3_base", "llcc_broadcast_base";
180 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;