1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments interconnect target module
10 - Tony Lindgren <tony@atomide.com>
13 Texas Instruments SoCs can have a generic interconnect target module
14 for devices connected to various interconnects such as L3 interconnect
15 using Arteris NoC, and L4 interconnect using Sonics s3220. This module
16 is mostly used for interaction between module and Power, Reset and Clock
17 Manager PRCM. It participates in the OCP Disconnect Protocol, but other
18 than that it is mostly independent of the interconnect.
20 Each interconnect target module can have one or more devices connected to
21 it. There is a set of control registers for managing the interconnect target
22 module clocks, idle modes and interconnect level resets.
24 The interconnect target module control registers are sprinkled into the
25 unused register address space of the first child device IP block managed by
26 the interconnect target module. Typically the register names are REVISION,
27 SYSCONFIG and SYSSTATUS.
31 pattern: "^target-module(@[0-9a-f]+)?$"
39 - ti,sysc-omap4-simple
58 Interconnect target module control registers consisting of
59 REVISION, SYSCONFIG and SYSSTATUS registers as defined in the
60 Technical Reference Manual for the SoC.
66 Interconnect target module control register names consisting
67 of "rev", "sysc" and "syss".
77 - enum: [ sysc, syss ]
80 description: Target module power domain if available.
85 Target module clocks consisting of one functional clock, one
86 interface clock, and up to 8 module specific optional clocks.
87 Some modules may have only the functional clock, and some have
88 no configurable clocks.
94 Target module clock names like "fck", "ick", "optck1", "optck2"
95 if the clocks are configurable.
97 - enum: [ ick, fck, sys_clk ]
100 - enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ]
117 Target module reset bit in the RSTCTRL register if wired for the module.
118 Note that the other reset bits should be mapped for the child device
124 Target module reset names in the RSTCTRL register, typically named
125 "rstctrl" if only one reset bit is wired for the module.
140 description: Mask of supported register bits for the SYSCONFIG register
141 $ref: /schemas/types.yaml#/definitions/uint32
144 description: List of hardware supported idle modes
145 $ref: /schemas/types.yaml#/definitions/uint32-array
148 description: List of hardware supported idle modes
149 $ref: /schemas/types.yaml#/definitions/uint32-array
152 description: Mask of supported register bits for the SYSSTATUS register
153 $ref: /schemas/types.yaml#/definitions/uint32
156 description: Delay needed after OCP softreset before accessing SYCONFIG
162 description: Interconnect target module shall not be reset at init
166 description: Interconnect target module shall not be idled at init
170 description: Interconnect target module shall not be idled
174 description: Interconnect module name to use with legacy hwmod data
175 $ref: /schemas/types.yaml#/definitions/string
184 additionalProperties:
189 #include <dt-bindings/bus/ti-sysc.h>
190 #include <dt-bindings/clock/omap4.h>
192 target-module@2b000 {
193 compatible = "ti,sysc-omap2", "ti,sysc";
194 ti,hwmods = "usb_otg_hs";
198 reg-names = "rev", "sysc", "syss";
199 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
201 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
202 SYSC_OMAP2_SOFTRESET |
203 SYSC_OMAP2_AUTOIDLE)>;
204 ti,sysc-midle = <SYSC_IDLE_FORCE>,
207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
210 <SYSC_IDLE_SMART_WKUP>;
212 #address-cells = <1>;
214 ranges = <0 0x2b000 0x1000>;