1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
13 This binding describes the dependencies (clocks, resets, power domains) which
14 need to be turned on in a sequence before communication over the AHB bus
17 Additionally, the reg property is used to pass to the driver the location of
18 two sadly undocumented registers which need to be poked as part of the sequence.
20 The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
21 controllers, a hexagon core, and a clock controller which provides clocks for
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
33 - description: SSCAON_CONFIG1 registers
37 - const: mpm_sscaon_config0
38 - const: mpm_sscaon_config1
62 - description: CX power domain
63 - description: MX power domain
72 - description: Main reset
74 SSC Branch Control Register reset (associated with the ssc_xo and
83 $ref: /schemas/types.yaml#/definitions/phandle-array
84 description: describes how to locate the ssc AXI halt register
87 - description: Phandle reference to a syscon representing TCSR
88 - description: offset for the ssc AXI halt register
105 additionalProperties:
110 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
111 #include <dt-bindings/clock/qcom,rpmcc.h>
112 #include <dt-bindings/power/qcom-rpmpd.h>
115 #address-cells = <1>;
118 // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
119 ssc_ahb_slave: bus@10ac008 {
120 #address-cells = <1>;
124 compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
125 reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
126 reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
129 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
131 <&gcc AGGRE2_SNOC_NORTH_AXI>,
133 <&gcc SSC_CNOC_AHBS_CLK>;
134 clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
136 resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
137 reset-names = "ssc_reset", "ssc_bcr";
139 power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
140 power-domain-names = "ssc_cx", "ssc_mx";
142 qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;