Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
   8
   9 maintainers:
  10   - Liu Ying <victor.liu@nxp.com>
  11
  12 description: |
  13   i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
  14   sitting together with the PHYs.  It is not the same as the MSI bus coming
  15   from i.MX8 System Controller Unit (SCU) which is used to control power,
  16   clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
  17
  18   i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
  19   that is, MSI clock and AHB clock, need to be enabled so that peripherals
  20   connected to the bus can be accessed. Also, the bus is part of a power
  21   domain. The power domain needs to be enabled before the peripherals can
  22   be accessed.
  23
  24   Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
  25   like I2C controller, PWM controller, MIPI DSI controller and Control and
  26   Status Registers (CSR) module, are accessed through the bus.
  27
  28   The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
  29   pixel link MSI bus controller and does not allow SCFW user to control it.
  30   So, the controller's registers cannot be accessed by SCFW user. Hence,
  31   the interrupts generated by the controller don't make any sense from SCFW
  32   user's point of view.
  33
  34 allOf:
  35   - $ref: simple-pm-bus.yaml#
  36
  37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
  38 select:
  39   properties:
  40     compatible:
  41       contains:
  42         enum:
  43           - fsl,imx8qxp-display-pixel-link-msi-bus
  44           - fsl,imx8qm-display-pixel-link-msi-bus
  45   required:
  46     - compatible
  47
  48 properties:
  49   compatible:
  50     items:
  51       - enum:
  52           - fsl,imx8qxp-display-pixel-link-msi-bus
  53           - fsl,imx8qm-display-pixel-link-msi-bus
  54       - const: simple-pm-bus
  55
  56   reg:
  57     maxItems: 1
  58
  59   interrupts:
  60     maxItems: 1
  61
  62   clocks:
  63     items:
  64       - description: master gated clock from system
  65       - description: AHB clock
  66
  67   clock-names:
  68     items:
  69       - const: msi
  70       - const: ahb
  71
  72 patternProperties:
  73   "^.*@[0-9a-f]+$":
  74     description: Devices attached to the bus
  75     type: object
  76
  77     required:
  78       - reg
  79
  80 required:
  81   - compatible
  82   - reg
  83   - clocks
  84   - clock-names
  85   - power-domains
  86
  87 unevaluatedProperties: false
  88
  89 examples:
  90   - |
  91     #include <dt-bindings/clock/imx8-lpcg.h>
  92     #include <dt-bindings/firmware/imx/rsrc.h>
  93     bus@56200000 {
  94         compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
  95         reg = <0x56200000 0x20000>;
  96         #address-cells = <1>;
  97         #size-cells = <1>;
  98         interrupt-parent = <&dc0_irqsteer>;
  99         interrupts = <320>;
 100         ranges;
 101         clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>,
 102                  <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>;
 103         clock-names = "msi", "ahb";
 104         power-domains = <&pd IMX_SC_R_DC_0>;
 105
 106         syscon@56221000 {
 107             compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
 108             reg = <0x56221000 0x1000>;
 109             clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
 110             clock-names = "ipg";
 111
 112             pxl2dpi {
 113                 compatible = "fsl,imx8qxp-pxl2dpi";
 114                 fsl,sc-resource = <IMX_SC_R_MIPI_0>;
 115                 power-domains = <&pd IMX_SC_R_MIPI_0>;
 116
 117                 ports {
 118                     #address-cells = <1>;
 119                     #size-cells = <0>;
 120
 121                     port@0 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         reg = <0>;
 125
 126                         mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
 127                             reg = <0>;
 128                             remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
 129                         };
 130
 131                         mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
 132                             reg = <1>;
 133                             remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
 134                         };
 135                     };
 136
 137                     port@1 {
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         reg = <1>;
 141
 142                         mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
 143                             reg = <0>;
 144                             remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
 145                         };
 146
 147                         mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
 148                             reg = <1>;
 149                             remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
 150                         };
 151                     };
 152                 };
 153             };
 154
 155             ldb {
 156                 #address-cells = <1>;
 157                 #size-cells = <0>;
 158                 compatible = "fsl,imx8qxp-ldb";
 159                 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
 160                          <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
 161                 clock-names = "pixel", "bypass";
 162                 power-domains = <&pd IMX_SC_R_LVDS_0>;
 163
 164                 channel@0 {
 165                     #address-cells = <1>;
 166                     #size-cells = <0>;
 167                     reg = <0>;
 168                     phys = <&mipi_lvds_0_phy>;
 169                     phy-names = "lvds_phy";
 170
 171                     port@0 {
 172                         reg = <0>;
 173
 174                         mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
 175                             remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
 176                         };
 177                     };
 178
 179                     port@1 {
 180                         reg = <1>;
 181
 182                         /* ... */
 183                     };
 184                 };
 185
 186                 channel@1 {
 187                     #address-cells = <1>;
 188                     #size-cells = <0>;
 189                     reg = <1>;
 190                     phys = <&mipi_lvds_0_phy>;
 191                     phy-names = "lvds_phy";
 192
 193                     port@0 {
 194                         reg = <0>;
 195
 196                         mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
 197                             remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
 198                         };
 199                     };
 200
 201                     port@1 {
 202                         reg = <1>;
 203
 204                         /* ... */
 205                     };
 206                 };
 207             };
 208         };
 209
 210         clock-controller@56223004 {
 211             compatible = "fsl,imx8qxp-lpcg";
 212             reg = <0x56223004 0x4>;
 213             #clock-cells = <1>;
 214             clocks = <&mipi_lvds_0_ipg_clk>;
 215             clock-indices = <IMX_LPCG_CLK_4>;
 216             clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk";
 217             power-domains = <&pd IMX_SC_R_MIPI_0>;
 218         };
 219
 220         phy@56228300 {
 221             compatible = "fsl,imx8qxp-mipi-dphy";
 222             reg = <0x56228300 0x100>;
 223             clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
 224             clock-names = "phy_ref";
 225             #phy-cells = <0>;
 226             fsl,syscon = <&mipi_lvds_0_csr>;
 227             power-domains = <&pd IMX_SC_R_MIPI_0>;
 228         };
 229     };