1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
18 another: from CPU to SoC peripherals and between some SoC peripherals
19 (mostly between peripheral devices and RAM, but also between DMA and
20 some peripherals). In case of any protocol error, device not responding
21 an IRQ is raised and a faulty situation is reported to the AXI EHB
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
37 - description: AXI EHB MMIO system controller registers
45 '#interconnect-cells':
49 $ref: /schemas/types.yaml#/definitions/phandle
50 description: Phandle to the Baikal-T1 System Controller DT node
57 - description: Main Interconnect uplink reference clock
65 - description: Main Interconnect reset line
71 unevaluatedProperties: false
84 #include <dt-bindings/interrupt-controller/mips-gic.h>
87 compatible = "baikal,bt1-axi", "simple-bus";
88 reg = <0x1f05a000 0x1000>,
90 reg-names = "qos", "ehb";
93 #interconnect-cells = <1>;
99 interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&ccu_axi 0>;
102 clock-names = "aclk";
104 resets = <&ccu_axi 0>;
105 reset-names = "arst";