1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
13 This document defines device tree bindings for the Synopsys DWC
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
31 - rockchip,rk3568-dwc-ahci
32 - rockchip,rk3588-dwc-ahci
33 - const: snps,dwc-ahci
39 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
45 unevaluatedProperties: false
48 "^sata-port@[1-9a-e]$": false
59 - $ref: snps,dwc-ahci-common.yaml#
65 - rockchip,rk3588-dwc-ahci
82 - rockchip,rk3568-dwc-ahci
93 unevaluatedProperties: false
97 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
98 #include <dt-bindings/interrupt-controller/arm-gic.h>
99 #include <dt-bindings/ata/ahci.h>
100 #include <dt-bindings/phy/phy.h>
103 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
104 reg = <0xfe210000 0x1000>;
105 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
106 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
107 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
108 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
109 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
110 ports-implemented = <0x1>;
111 #address-cells = <1>;
116 hba-port-cap = <HBA_PORT_FBSCP>;
117 phys = <&combphy0_ps PHY_TYPE_SATA>;
118 phy-names = "sata-phy";
119 snps,rx-ts-max = <32>;
120 snps,tx-ts-max = <32>;